1. Field of the Present Invention
The present invention relates to a method of manufacturing a semiconductor device and, more particularly, to a method of manufacturing a semiconductor device, utilizing CMP (Chemical Mechanical Polishing) to thereby form in two polishing steps a via-plug in an inter-layer insulating film for interconnecting an upper layer wiring and a lower layer wiring.
The present application claims priority of Japanese Patent Application No.2001-171812 filed on Jun. 6, 2001, which is hereby incorporated by reference.
2. Description of the Related Art
An LSI (Large Scale Integration) such as a microprocessor or a memory known as a representative of a semiconductor device has been more and more fine-patterned in size of individual elements thereof with an improvement in integration density, which is accompanied by finer patterning of a semiconductor region of each of the elements. Also, in formation of a wiring to connect such semiconductor regions, if the wiring is formed only in a plane direction of a semiconductor substrate, a wiring density cannot be high, to solve such problem a multi-layer wiring technology has been developed for forming the wiring also in a thickness direction through a plurality of layers.
In such the LSI, a resistance of the wiring has a significant effect on characteristics such as an operating speed, so that the wiring is desired to be low in resistance. Conventionally, as a material of the wiring in semiconductor devices including an LSI, aluminum (Al) or an Al-based metal made of Al mainly has generally been used because of their good electrical characteristics, processibility, and a like. The Al-based metals, however, have an disadvantage of poor electro-migration resistance, stress-migration resistance, and a like. To solve this problem, rather than the Al-based metals, copper (Cu) or a Cu-based metal made of Cu mainly is employed presently because of their excellence in electro-migration resistance, stress-migration resistance, and the like.
The Cu-based metal, however, is stable chemically when it is formed as a film, so that a Cu-based metal film, once formed, cannot easily be patterned into a desired shape of a wiring by etching as compared to an Al-based metal film. To solve this problem, a so-called Damascene wiring technology is employed, whereby when forming a wiring using a Cu-based metal, a wiring trench is formed beforehand in an interlayer insulating film formed on a semiconductor substrate, then a Cu-based metal film is formed all over the surface including this wiring trench, and then an unnecessary part of this Cu-based metal film on the inter-layer insulating film is removed by CMP, thus providing the wiring made of the Cu-based metal film which is left (embedded) only in the wiring trench.
A semiconductor device having a multi-layer wiring construction formed by this Damascene wiring technology is disclosed, for example, in Japanese Patent Application Laid-open No. 2000-277612. To manufacture this semiconductor device, as shown in FIG. 9, a first inter-layer insulating film 54 made of silicon oxide (SiO2) or a like is formed on a semiconductor substrate 51 via an insulating film 52 made of silicon oxide or the like and an etching stopper film 53 made of silicon nitride (SiN), in a wiring trench 55 in which first inter-layer insulating film 54 is formed a lower layer wiring 57 (first layer wiring) made of a Cu film as embedded therein via a barrier film 56. Also, on the first inter-layer insulating film 54 is formed via an etching stopper film 58, a second inter-layer insulating film 60, in a wiring trench (via-hole 59 in this case) in which the second inter-layer insulating film 60 is formed via a barrier film 61 a conductive plug (via-plug 63) made of a Cu film. Further, on the second inter-layer insulating film 60 is formed via a barrier film 64 an upper layer wiring 65 (second layer wiring) made of a Cu film. In this configuration, the barrier films 56, 64, and a like serve as a diffusion preventing film for preventing Cu from diffusing downward.
As can be seen from the above, in the conventional semiconductor device shown in FIG. 9, in the via-hole 59 in the second inter-layer insulating film 60 covering the lower layer wiring 57 made of the Cu film is formed the via-plug 63 made of the Cu film by the Damascene wiring technology, thus interconnecting the lower layer wiring (first layer wiring) 57 and the upper layer wiring (second layer wiring) 65. Although in this conventional example, the lower layer wiring (first layer wiring) 57 and the upper layer wiring (second layer wiring) 65 are interconnected through the via-plug 63, further a third layer and subsequent ones of wirings may be formed vertically and interconnected through a via-plug in some cases. In some microprocessors representative of an LSI, a multi-layer wiring construction is implemented including up to eight or nine layers.
To manufacture a semiconductor device having the multi-layer wiring construction using the above-mentioned Damascene wiring technology, the following method utilizing CMP is employed. This method is described below along the steps thereof with reference to FIGS. 10A-10D.
First, as shown in FIG. 10A, the semiconductor substrate 51 is prepared on a surface of which are formed the insulating film 52 made of silicon oxide or the like, the etching stopper film 53 made of silicon nitride or a like, and the first inter-layer insulating film 54 made of silicon oxide or the like sequentially. Next, a known photolithographic method is utilized to thereby form the wiring trench 55 in the first inter-layer insulating film 54, in which wiring trench 55 is then embedded a Cu film via the barrier film 56 made of tantalum (Ta) to thereby form the lower layer wiring 57. To form this lower layer wiring 57, specifically the Ta film and the Cu film are formed sequentially throughout the surface including the wiring trench 55 after this wiring trench 55 is formed in the first inter-layer insulating film 54 beforehand, then an unnecessary part of the Cu film on the first inter-layer insulating film 54 is removed by CMP until the Ta film is exposed, and then an unnecessary part of the Ta film on the first inter-layer insulating film 54 is removed similarly by CMP, thus leaving the Cu film only in the wiring trench 55 via the barrier film 56. Next, as shown in FIG. 10B, the second inter-layer insulating film 60 made of silicon oxide is formed throughout the surface via the etching stopper film 58 made of silicon nitride, on which second inter-layer insulating film 60 is formed a photo-resist film 67 except in a region in which the via-hole 59 is to be formed.
Next, as shown in FIG. 10C, using the photo-resist film 67 as a mask, the second inter-layer insulating film 60 and the etching stopper film 58 are etched sequentially to form the via-hole 59, through which the lower layer wiring 57 is to be exposed.
Next, as shown in FIG. 10D, the photo-resist film 67 is removed, then the barrier film 61 made of Ta is formed by sputtering throughout the surface including the via-hole 59, and then a Cu film 70 is formed by plating throughout the surface. Specifically, however, a seed film (not shown) for plating purpose made of a thin Cu film is formed beforehand by sputtering on the barrier film 61 and then Cu is plated onto this plating seed film.
Next, as shown in FIG. 10E, to form the via-plug in the second inter-layer insulating film 60, first an unnecessary part of the Cu film 70 on the second inter-layer insulating film 60 is removed by CMP until the barrier film 61 is exposed (first polishing step). At this first polishing step, CMP is carried out under such conditions that the Cu film 70 may have a higher polishing rate than the barrier film 61.
Next, as shown in FIG. 10F, the barrier film 61 on the second inter-layer insulating film 60 is removed by CMP to leave the Cu film 70 only in the via-hole 59, thus forming the via-plug 63 (second polishing step). At this second polishing step, CMP has conventionally been carried out under such conditions that a polishing liquid employed may have an addition of about 1.5 weight-percent or more of, in particular, hydrogen peroxide (H2O2), which is an oxidizing agent. This CMP method has also been carried out under such conditions that a pressure of about 4 Psi (Pounds per square inch) or less may be applied on the barrier film 61. Conventionally, such setting of the quantity of a hydrogen peroxide added (that is, concentration) has been considered to be preferably because it reduces the frictional force on the barrier film 61 during CMP. Also, such setting of the pressure has been considered preferably because it relaxes polishing of the barrier film 61.
Next, the upper layer wiring 65 (second layer wiring) made of the Cu film is formed on the second inter-layer insulating film 60 via the barrier film 64, thus completing a semiconductor device having such a multi-layer wiring construction as shown in FIG. 9.
The conventional semiconductor device manufacturing method, however, has the following problem in the second polishing step for forming the via-plug 63 using CMP.
First, by this semiconductor device manufacturing method, in the second step for forming the via-plug 63 which interconnects the lower layer wiring 57 and the upper layer wiring 65, as mentioned above, about 1.5 weight-percent or more of hydrogen peroxide is added to the polishing liquid employed in CMP, thus taking long time to polish the barrier film 61. That is, by using such a polishing liquid in CMP, as mentioned above, the frictional force on the barrier film 61 can be reduced to thereby give an advantage of uniform polishing of the barrier film 61, which, however, gives rise to such a problem that the polishing rate of the barrier film 61 is decreased to thereby take long time in polishing, thus deteriorating throughput.
Also, by the conventional semiconductor device manufacturing method, in the second polishing step for forming the via-plug 63 which interconnects the lower layer wiring 57 and the upper layer wiring 65, the CMP processing of the barrier film 61 involves application of a pressure of about 4 Psi on the barrier film 61 on the second inter-layer insulating film 60, so that peripheral portions of the semiconductor device, which have a large step, has a residue of the barrier film 64 thereon, thus giving rise to a problem of poor surface uniformity.
That is, as shown in FIG. 11, generally when an insulating film or a conductive film is stacked repeatedly on the semiconductor substrate 51, a step is inevitably formed particularly at a peripheral portion 51A of the semiconductor substrate 51 as shown in FIG. 12. Therefore, if the pressure is set at about 4 Psi to relax polishing as mentioned above, the polishing rate of the barrier film 61 is decreased, so that the barrier film 61 is liable to be left at the peripheral portion 51A even after CMP is carried out thereon, thus deteriorating the surface uniformity. Such a residue of the barrier film 64 may give poor close contact between the second inter-layer insulating film 60 and any other insulating film such as an etching stopper film 58, if formed thereon in the post-processing, thus easily giving rise to peel-off of the other insulating film.
Further, by the conventional semiconductor device manufacturing method, in the second polishing step for forming the via-plug 63 which interconnects the lower layer wiring 57 and the upper layer wiring 65, the CMP processing of the barrier film 61 generates a recess in the via-plug 63, thus giving rise to a problem of open circuiting of a via-chain.
That is, as compared to a density of wirings 73 such as the lower layer or upper layer wiring formed on the semiconductor substrate 51 as shown in FIG. 13A, that of the via-plugs 63 formed therein is small by one digit or more as shown in FIG. 13B The CMP abrasive liquid, therefore, is concentrated at an exposed portion of the via-plugs 63 formed as rather isolated, so that they are etched off in a concentrated manner as shown in FIG. 14, thus forming a recess 69 therein. As such, the via-plugs 63 fail to connect to the upper layer wiring, so that the upper layer and lower layer wirings are nonconductive to each other, thus suffering from open-circuiting therebetween. Also, the recess 69 is clogged with abrasive grain contained in the polishing liquid to resultantly give poor contact between the upper layer and lower layer wirings, thus giving open-circuiting therebetween similarly.